The overall structure of an FPGA is described by Freeman in U.S. Patent Re34,363. An FPGA includes configurable logic blocks and a configurable interconnect structure for connecting the logic blocks and otherwise routing signals through the FPGA. An FPGA may be configured to perform a particular function by turning on and off particular transistors in the FPGA to select functions performed by the logic blocks of the FPGA and to connect the logic blocks to each other through interconnect lines. One FPGA architecture with which the present invention will work is described by Tavana et al in U.S. patent application Ser. No. 08/222,138 M-2257-1N! entitled FPGA Architecture with Repeatable Tiles Including Routing Matrices and Logic Matrices. The subject matter of this patent application is incorporated herein by reference.
It is common to use a single bus line for alternatively providing one of several signals to a circuit element. When a bus line is used, a control system must assure that only one driver uses the bus at one time. (A bus line may alternatively be used to provide a signal from a single source, or may be used to generate a wired-AND function by connecting a pull-up resistor and many pull-down signal sources of which none or many may be connected simultaneously.) FPGA integrated circuit chips having a tristate buffer structure for alternately placing multiple signals onto one bus line are available in the XC4000 and XC5200 families of devices available from Xilinx, Inc., assignee of the present invention. The tristate buffer feature of the Xilinx XC4000 family of products is described in the Xilinx 1994 Data Book at pages 2-16 and 2-24. The XC5200 family is illustrated in the XC5200 Logic Cell Array Family Technical Data published October 1995, pages 1-20. The tristate buffer is illustrated at pages 5 and 11.
In the Xilinx XC4000 and XC5200 families of FPGA devices, certain of the interconnect lines can serve as bus lines. Output terminals of several tristate buffers are connected to these lines and a control structure is present in the FPGA for selecting which tristate buffer places its signal onto the interconnect line.
FIG. 1 shows a tristate buffer structure including two line segments O1 and O2 which may or may not be connected together using programmable connector C2 to form a single bus line, and eight tristate buffers B1 through B8 for alternatively driving the line segments. Each buffer B1 through B8 typically receives an input signal from a different configurable logic block of the FPGA. (These configurable logic blocks are not shown in FIG. 1.) The bus line segments O1 and O2 can also be connected to terminals of configurable logic blocks via local interconnect line segments. FIG. 1 shows two configurable logic blocks, CLB1 and CLB2, which can be programmably connected to line segments O1 and O2 respectively. Programmable connectors such as C1, C1a, C1b, C1c, and C3 make these connections. Also, programmable connector C2 connects line segments O1 and O2 together. A control system, not shown, places an enable signal (may be active high or active low) on a selected tristate enable line E1 through E8 and thereby connects the selected input line I1 through I8 to its corresponding bus line segment O1 or O2. If programmable connector C2 is not connecting segments O1 and O2 together, each segment may receive its own driving signal.
FIG. 2 shows symbols used in the drawings, including a small black dot to indicate a permanent connection, a white circle to indicate a programmable connection not connected, and a black circle to indicate a programmable connection that is connected.
FIG. 3 shows part of a logic design which a user may wish to implement in an FPGA. In this example, the design has seven signals S1 through S7 to be alternatively placed onto a bus BUS1, which provides an input signal to a logic unit L1. Software is available to receive a user's design, including a structure such as illustrated in FIG. 3, and to select components of an FPGA which will implement each portion of the design. This software typically partitions the user's design into portions which will be implemented in a CLB and its related tristate buffers (called partitioning or mapping), then selects particular CLBs and tristate buffers to implement each portion (called placement), and finally selects interconnect lines to connect the pieces together according to the user's design (called routing). Sometimes, because of other logic not shown in FIG. 3, the placement step may choose to skip a tristate buffer when placing the logic for generating signals S1 through S7.
FIG. 4 shows an example implementation of the user's design of FIG. 3 in the FPGA structure of FIG. 1. In order to alternatively connect seven signal lines to the same bus, segments O1 and O2 are connected together by turning on connector C2. The user's logic represented in FIG. 3 by L1 is implemented in FIG. 4 by CLB1. Thus connectors C1 and C1b are turned on to connect segment O1 to CLB1. Connector C3 is not turned on, since CLB2 is not used to implement the design of FIG. 3. Because of placement and possible other considerations, the signal S7 of FIG. 3 will be generated in a non-contiguous logic block and placed onto signal line 18. Thus, buffer B7 is disabled by connecting enable line E7 to ground through connector C4. During operation, the control structure (not shown) places a high signal onto one of E1 through E6 and E8 to turn on one of the corresponding buffers B1 through B6 and B8. The selected signal S1 through S7 placed on line I1 through I6 and 18 is then provided to CLB1.
The structure of FIGS. 1 and 4 requires that each of buffers B1 through B8 be of sufficient size to drive any other circuit elements that may be connected to bus lines O1 and O2. If many input signals may be buffered onto the bus and many circuit elements may be driven by the bus, the size of the structure of FIG. 1 can be undesirably large or else the speed of signal propagation can be undesirably slow.